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1st IEEE Federative Event on Design for Robustness (FEDfRo)
(FEDfRo’16)
July 4-6, 2016
Hotel Eden Roc, Sant Feliu de Guixols, Catalunya, Spain

http://tima.imag.fr/conferences/fedfro/fedfro16/

NEW INITIATIVE

Scope

Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications.

Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security.

These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo) was initiated to meet this goal, and was established by bringing together:

IOLTS: the 22nd International On-Line Testing Symposium
http://tima.imag.fr/conferences/iolts/iolts16/
a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems; 

IMSTW: the 21st International Mixed-Signal Testing Workshop
http://tima.imag.fr/conferences/imstw/imstw16/
a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits; 

IVSW: the 1st International Verification and Security Workshop
http://tima.imag.fr/conferences/ivsw/ivsw16/
a new IEEE forum addressing all Verification and Security issues associated with electronic systems.

The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.  


Committee

Coordinators:

Michael Nicolaidis
TIMA Laboratory
Grenoble, France
Tel: +33 (0) 476 574696
michael.nicolaidis@imag.fr

Florence Azais
LIRMM
Montpellier, France
Tel: +33 (0) 467 418625
florence.azais@lirmm.fr

Magdy Abadir
Abadir and  Associates
Austin, Texas USA
Tel: +1 (512) 5762701
magdy.abadir@gmail.com

Publicity chair:
Stefano Di Carlo
Polotecnico di Torino
Torino, Italy
Tel: +39 (0) 115 647080
stefano.dicarlo@polito.it

For more information, visit us on the web at: http://tima.imag.fr/conferences/fedfro/fedfro16/

The 1st IEEE Federative Event on Design for Robustness (FEDfRo) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR
Michael Purtell
Intersil
- USA
Tel. +1-408-372-6015
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR

Synopsys, Inc.
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC
André IVANOV
U. of British Columbia - Canada
Tel. +1
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC 
Gumma University - Japan
Tel.+81-277-30-1111
E-mail k-hatayama@el.gunma-u.ac.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com


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