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1st IEEE Federative Event on Design for Robustness (FEDfRo) |
NEW INITIATIVE |
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Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications. IOLTS: the 22nd International On-Line Testing Symposium |
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Committee | |
Coordinators: Michael Nicolaidis Florence Azais Magdy Abadir Publicity chair: |
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For more information, visit us on the web at: http://tima.imag.fr/conferences/fedfro/fedfro16/ |
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The 1st IEEE Federative Event on Design for Robustness (FEDfRo) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
IEEE
Computer Society- Test Technology Technical Council |
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